A. Field of the Invention
This invention relates to priority circuits used in conjunction with memory access systems. More particularly, it relates to those memory systems having multiport access capabilities wherein priority logic circuits are used to determine the sequential order in which requests have been presented.
B. Prior Art
In the past, priority circuits have been used to determine the sequential order which requestors have been accepted without conflict. Thus, as each memory request was made, earlier priority circuits merely placed them in the sequential order in which they were received so that they gained memory access in the same sequence in which the requests were made. Further, these request signals were temporarily stored in a register from which they were individually serviced as a memory port became available. The priority request register then was first filled with requests for memory and thereafter emptied in sequence until the last request was handled. At that time, the register was refilled and the sequence was repeated. However, as memory speed was increased, it soon became apparent that a relatively substantial amount of time was wasted between the granting of the last request of the previous group and the first request in the next group refill. Thus, no memory requests were being handled as the register was being refilled with the next group of request signals. In the present instance, this time gap was unacceptable.